Practical Tips to Optimize Code for CPU Pipelines#

Stages of a Typical Pipeline#

Many modern CPUs use a pipeline with five classic stages, though real implementations often split or combine them:

1. Instruction Fetch (IF): The CPU fetches the next instruction from memory or cache.
2. Instruction Decode (ID): The fetched instruction is decoded, and the CPU determines what tasks must be done.
3. Execute (EX): The functional units (ALU, FPU, etc.) carry out the operation.
4. Memory Access (MEM): If the instruction requires data from memory or writes to memory, it occurs here.
5. Write Back (WB): The result of the instruction is written to the register file.

In reality, modern superscalar or pipeline designs have many more subtleties. Nevertheless, understanding these classic stages is a jumping-off point. Each stage might introduce different kinds of pipeline hazards.

Pipeline Hazards#

A hazard is any situation that disrupts the flow of instructions in the pipeline. There are three primary types:

1. Structural Hazards: Occur when hardware resources (e.g., memory buses, functional units) are insufficient for executing all concurrent operations.
2. Data Hazards: Happen when instructions depend on the results of previous instructions that haven’t finished yet.
3. Control Hazards: Occur due to branching or other control flow changes that alter which instruction comes next.

Table: Common Pipeline Hazards and Their Causes

Register Dependencies#

Data hazards often appear when instructions need the results of previous instructions. For instance:

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int compute(int x, int y) {
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    int a = x + 1;
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    int b = a * y;
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    return b;
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}

Conceptually, b depends on a, which depends on x. If a is not yet computed when b is ready to multiply, the pipeline must stall. Modern CPUs try to mitigate this with out-of-order execution, but reordering code, using different registers, or structuring computations can help further.

Cache and Memory Optimizations#

Memory access patterns strongly influence performance because memory reads can cause pipeline stalls if data is not readily available:

• Spatial Locality: Access memory in contiguous chunks.
• Temporal Locality: Reuse data that remains in cache.
• Prefetching: Trigger hardware or software-based prefetch instructions to bring data into cache before it’s needed.

Data layout in memory is particularly important in loops performing arithmetic on large arrays. Ensure consecutive elements are used in sequence to boost cache efficiency.

Minimizing Branches#

Each time the CPU encounters a conditional branch, it must guess which path to execute so the pipeline remains full. A misprediction can result in a significant performance penalty. You can reduce the negative impact of branches by:

1. Consolidating Conditions: Combine multiple if-conditions if possible.
2. Avoiding Deep if-else Chains: Flatten the control flow where you can.
3. Using Predication (in architectures that support it): Compiler intrinsics or instructions that conditionally execute without branching.

In many high-level languages, you can sometimes replace a small if-else with a conditional assignment:

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// Potentially more predictable:
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int val = (condition) ? x : y;

Rather than:

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int val;
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if (condition) {
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    val = x;
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} else {
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    val = y;
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}

Branch Hints and Patterns#

Some compilers let you supply hints or built-ins (e.g., __builtin_expect in GCC) to indicate which branch is more likely:

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if (__builtin_expect(condition, 1)) {
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    // Likely taken
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} else {
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    // Less likely
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}

But always rely on actual profiling data—guesswork can mislead your optimizations.

Superscalar Execution#

Modern CPUs can decode and execute multiple instructions per cycle, but only if there are no data hazards between them. The compiler’s instruction scheduling tries to group independent instructions free of dependency stalls:

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; Hypothetical assembly snippet
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mov eax, [rdi]    ; 1) Load data from pointer rdi
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mov ebx, 10       ; 2) Immediate load, no dependency on the above
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add eax, ebx      ; 3) Now depends on the result of 1 and 2, can’t run in parallel with them

In a superscalar design, instructions 1) and 2) could be decoded simultaneously if the hardware resources are available and if each instruction uses different functional units.

Out-of-Order Execution#

CPUs can reorder instructions internally to hide latencies. For example, if an instruction is waiting for a memory load, the CPU may skip ahead, execute subsequent independent instructions, and come back later to finish. While this can help hide latencies, it still relies on having enough independent work available. Organizing your code to have as many independent instructions as possible is beneficial.

Compiler Auto-Vectorization#

When you compile with optimizations enabled (e.g., -O3), the compiler tries to vectorize loops automatically. Consider a loop doing integer addition on arrays:

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for (int i = 0; i < N; i++) {
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    C[i] = A[i] + B[i];
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}

The compiler might generate SIMD instructions (e.g., SSE, AVX) to process multiple elements in a single instruction. However, it may fail if the loop is too complex or if there are potential pointer aliasing issues. Helpful hints include using keywords like restrict in C/C++ to assure the compiler that pointers do not overlap.

Intrinsics for Fine-Grained Control#

For more advanced optimization, you can use intrinsics like _mm_add_ps (for SSE) or _mm256_mul_pd (for AVX) to directly write vector instructions in C/C++. This approach allows granular control, but it’s less portable and can be verbose:

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#include <immintrin.h>
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void vec_add(float* A, float* B, float* C) {
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    __m256 va = _mm256_loadu_ps(A);  // Load 8 floats
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    __m256 vb = _mm256_loadu_ps(B);  // Load 8 floats
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    __m256 vc = _mm256_add_ps(va, vb); // Add them
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    _mm256_storeu_ps(C, vc);        // Store result
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}

Such code is specialized for specific microarchitectures and data sizes. But in tight performance-critical sections, intrinsics can be worth the extra effort.

Software Pipelining#

Software pipelining tries to rearrange instructions so that different parts of the loop iteration can run in overlapped fashion. The compiler might unroll the loop and reorder instructions from multiple iterations:

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// Pseudo-code illustrating software pipelining
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for (i = 0; i < N; i++) {
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    LOAD X[i+1]
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    COMPUTE something with X[i]
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    STORE result for X[i-1]
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}

While the CPU does hardware-based out-of-order execution, carefully designing loops can still help ensure the pipeline remains busy.

Unrolling Loops#

Loop unrolling reduces loop overhead (branch checks, increments) and can expose more ILP:

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// Example: manually unrolled loop
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for (int i = 0; i < N; i += 4) {
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    sum += A[i];
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    sum += A[i + 1];
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    sum += A[i + 2];
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    sum += A[i + 3];
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}

However, excessive unrolling can bloat code size, hurt instruction cache performance, and reduce overall gains. Profiling is critical to striking a balance.

Precomputation Strategies#

If calculations or lookups repeat frequently, precompute them:

1. Constant Expressions: The compiler often handles these, but you can help by isolating them in global or static arrays.
2. Table Lookups: Transform complicated math (e.g., trigonometric functions) into table lookups if the domain is limited.
3. Evaluate Complex Conditionals Early: Precompute conditions or branch decisions in broader logic when possible.

Naive Implementation#

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void matmul_naive(int n, float* A, float* B, float* C) {
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    // C = A x B, square matrices of size n x n
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    for (int i = 0; i < n; i++) {
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        for (int j = 0; j < n; j++) {
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            float sum = 0.0f;
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            for (int k = 0; k < n; k++) {
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                sum += A[i * n + k] * B[k * n + j];
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            }
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            C[i * n + j] = sum;
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        }
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    }
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}

This version has three nested loops, resulting in O(n^3) complexity. Beyond that, it has poor cache locality because B is accessed in a non-contiguous way relative to the iteration order.

Optimized Implementation#

1. Block/Tile the Matrices: Break matrices into sub-blocks small enough to fit in cache.
2. Unroll Loops: Unroll the innermost loop.
3. Leverage SIMD: Use compiler auto-vectorization or intrinsics to process multiple elements at once.

Here is a simplified tiling approach:

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void matmul_blocked(int n, float* A, float* B, float* C, int blockSize) {
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    for (int iBlock = 0; iBlock < n; iBlock += blockSize) {
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        for (int jBlock = 0; jBlock < n; jBlock += blockSize) {
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            for (int kBlock = 0; kBlock < n; kBlock += blockSize) {
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                for (int i = iBlock; i < iBlock + blockSize && i < n; i++) {
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                    for (int j = jBlock; j < jBlock + blockSize && j < n; j++) {
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                        float sum = C[i*n + j];
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                        for (int k = kBlock; k < kBlock + blockSize && k < n; k++) {
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                            // Tighter memory locality benefits
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                            sum += A[i*n + k] * B[k*n + j];
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                        }
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                        C[i*n + j] = sum;
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                    }
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                }
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            }
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        }
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    }
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}

Tiling improves locality by limiting how data moves through cache. You can further unroll and vectorize the k loop to take advantage of SIMD instructions. The exact block size depends on cache sizes and memory architecture, so experimentation is crucial.

Inlining and Function Calls#

Excessive function calls can degrade performance if the call overhead becomes significant, especially in tight loops. Most compilers can inline small functions, particularly under higher optimization levels:

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inline int add_two(int x) {
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    return x + 2;
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}

Inlining can reduce overhead but also cause code bloat if overused, so examine performance trade-offs. Profilers can highlight whether function call overhead is a bottleneck.

Compiler Flags and Profile-Guided Optimization (PGO)#

Profile-Guided Optimization (PGO) uses runtime profiling data to guide compiler decisions, such as:

1. Where to inline
2. How to reorder basic blocks
3. Branch prediction hints

For example, with GCC:

1. Compile with -fprofile-generate.
2. Run the program with representative input data.
3. Re-compile with -fprofile-use to incorporate the profiling data.

PGO often yields performance boosts by focusing optimizations on the most frequently visited code paths.

Profiling Tools#

Accurate measurements guide your optimization journey. Popular choices include:

• perf on Linux
• VTune on Intel CPUs
• Instruments on macOS
• Linux perf_event for low-level performance counter access

A typical process is:

1. Compile with optimizations.
2. Run the profiler with representative workloads.
3. Examine hotspots, pipeline stalls, cache misses.
4. Iterate on code transformations to reduce those stalls and misses.

Microbenchmarks#

For small, repeated computations, microbenchmarks can be enlightening. Libraries like Google Benchmark (C++) or Criterion (Rust) manage timing, warm-up runs, and iteration counts, giving consistent results.

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#include <benchmark/benchmark.h>
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static void BM_MatMul(benchmark::State& state) {
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    int n = 512;
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    // Initialize matrices A, B, C
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    ...
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    for (auto _ : state) {
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        matmul_naive(n, A, B, C);
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    }
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}
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BENCHMARK(BM_MatMul);
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BENCHMARK_MAIN();

Be aware of synthetic benchmarks that do not reflect real-world performance. Always confirm that actual application throughput improves.

Cross-Platform Pipeline Differences#

Each vendor (Intel, AMD, ARM) implements slightly different pipeline depths, out-of-order engines, and instruction latencies. The same code can perform differently on each CPU generation. When performance is critical across multiple systems:

1. Use CPU Feature Detection: Choose the best instruction set (SSE, AVX, AVX2, AVX-512) at runtime.
2. Conditional Compilation: Provide specialized code paths for different architectures.
3. Benchmark on Multiple Hardware Targets: Avoid overfitting to a single CPU model.

Microarchitecture-Specific Hacks#

Professionals occasionally use microarchitecture “tricks,” such as:

• Optimizing for the Uop Cache (on certain Intel chips).
• Eliminating partial register stalls by zeroing out registers before using them.
• Instruction puns (e.g., SSE instructions used for integer operations for higher throughput on certain chips).

These can yield high performance in specialized domains but require thorough testing and maintenance. If the CPU microarchitecture changes, these optimizations might backfire.