Ready, Set, Render: Future Trends in NVIDIA and AMD GPU Architecture#

1.1 GPU vs. CPU: A Core Difference#

A Central Processing Unit (CPU) typically has a relatively small number of cores optimized for sequential serial processing. It is designed to handle a wide range of tasks, focusing on low-latency execution.

By contrast, a GPU features a vast number of smaller, more specialized cores designed for high-volume parallel computations. In essence, CPUs excel at variety and quick context switching, while GPUs thrive on repetitive, parallel tasks.

1.2 Parallelism and Throughput#

The core component that sets a GPU apart is its focus on data parallelism and throughput. Each GPU core can often handle a small part of an overall computation in parallel with thousands of other cores. It’s like having a massive workforce each doing a tiny piece of the puzzle simultaneously. This architecture offers enormous potential for speeding up tasks where parallelism is possible, such as matrix multiplications in deep learning or rendering pixel shaders in a video game.

2.1 Stream Multiprocessors (SM) or Compute Units (CU)#

On NVIDIA GPUs, the smallest programmable unit is often referred to as the Streaming Multiprocessor (SM). Within each SM, you’ll find:

• CUDA cores (or “shader processors”)
• Special function units (SFUs) for trigonometric operations
• Tensor Cores (on modern architectures) for AI workloads
• Warp/Wavefront schedulers and dispatch units

On AMD GPUs, these units are often called Compute Units (CUs) or Workgroup Processors (WGPs) in newer architectures such as RDNA. Each CU packs multiple processing elements, vector units, and cache memory essential for high throughput operations.

2.2 Memory Hierarchy#

A GPU’s memory hierarchy is another key to its performance:

1. Global Memory: The largest memory pool, but also the slowest.
2. Local/Shared Memory: Faster than global memory, used by threads within the same thread block (NVIDIA) or workgroup (AMD).
3. Caches: Including L1, L2, and specialized caches (e.g., texture cache, instruction cache).
4. Register File: Extremely fast, used to store data for the currently executing thread or wavefront.

When writing GPU kernels, how well you utilize these memory spaces directly affects performance. Balancing data fetches from global memory with efficient caching is vital.

3.1 From Fermi to Ampere#

NVIDIA’s modern GPU lineage can be traced from Fermi, released around 2010, through Kepler, Maxwell, Pascal, Volta, Turing, and finally Ampere and Ada Lovelace.

• Fermi (2010): Introduced a refined GPGPU approach with CUDA cores and a more accessible programming model.
• Kepler (2012): Improved efficiency and introduced dynamic parallelism.
• Maxwell (2014): Known for power efficiency and improved concurrency.
• Pascal (2016): Brought in higher clock speeds, improved architectural efficiency, and introduced the NVLink interconnect in data center GPUs.
• Volta (2017): Debuted Tensor Cores for deep learning tasks and introduced a new type of scheduling.
• Turing (2018): Introduced the first mainstream ray-tracing cores (RT Cores) and improved Tensor Core performance.

3.2 Ampere and Ada Lovelace#

Ampere (launched in 2020) expanded on Turing’s innovations:

• Third-Generation Tensor Cores: Double the throughput for FP16, bfloat16, and other data types.
• Second-Generation RT Cores: Introduced more efficient hardware-accelerated ray tracing.
• GDDR6X Memory (on certain models): Allowed higher memory bandwidth.

Following Ampere, NVIDIA’s Ada Lovelace architecture (notable in RTX 40 Series consumer GPUs) further optimized ray tracing, introduced new AI-driven upscaling capabilities with DLSS 3.0, and continued to push the boundaries of power/performance ratios. The Ada architecture also includes additional hardware scheduling improvements and better resource allocation across Tensor, RT, and CUDA cores.

3.3 Ray Tracing and Tensor Cores#

• Ray Tracing Cores: Accelerate the computation of bounding volume hierarchy (BVH) traversal and ray-triangle intersection tests.
• Tensor Cores: Specialize in dense linear algebra operations. Ideal for machine learning tasks like matrix multiplication in neural network training and inference.

These specialized hardware blocks offload tasks that would otherwise overwhelm the GPU’s general-purpose shader processors.

4.1 From GCN to RDNA#

AMD’s evolution in GPU design runs from the Graphics Core Next (GCN) architecture to RDNA and beyond:

• GCN (2011 - 2018): Focused on compute capabilities and introduced asynchronous compute technology. Used in multiple generations, from the Radeon HD 7000 series to Radeon RX Vega.
• Polaris (2016): Built on a refined GCN architecture, focusing on power efficiency and mainstream gaming performance.
• Vega (2017): Introduced High Bandwidth Memory (HBM2) in some models and expanded compute abilities.

4.2 RDNA 2 and RDNA 3#

• RDNA (2019): Shifted the focus toward gaming efficiency. Introduced improvements in IPC (instructions per clock) and clock speed.
• RDNA 2 (2020): Brought hardware-accelerated ray-tracing capabilities (Ray Accelerators) and introduced the Infinity Cache to reduce memory latency. This architecture powers the Radeon RX 6000 series and also GPUs in gaming consoles like the PlayStation 5 and Xbox Series X|S.
• RDNA 3 (2022/2023): Employs chiplet-based designs on certain SKUs and includes further refinements in ray tracing and AI-accelerated workloads. Offers next-gen Infinity Cache and improvements to the memory subsystem.

4.3 Infinity Cache and Other Key Technologies#

One of AMD’s standout features is the Infinity Cache, a large, high-speed cache that reduces the need to fetch data from slower GDDR memory. This design significantly cuts down latency and can boost frame rates in gaming and throughput in compute tasks. AMD also continues to push new technologies, including:

• Ray Accelerators: Dedicated hardware units for accelerating ray intersection calculations.
• Smart Access Memory: Allows CPUs to access all of a GPU’s VRAM.
• FSR (FidelityFX Super Resolution): A platform-agnostic upscaling solution to compete with NVIDIA’s DLSS.

5.1 CUDA: NVIDIA’s Flagship Programming Model#

CUDA (Compute Unified Device Architecture) is NVIDIA’s proprietary API and parallel computing platform. It allows developers to write programs in C, C++, Python, or other languages that offload compute kernels to the GPU.

Key CUDA features include:

• Kernel-based programming: Functions (kernels) launched on thousands of threads in parallel.
• Memory management: Distinction between host (CPU) and device (GPU) memory.
• Libraries: CuBLAS, CuDNN, Thrust, among others, provide highly optimized routines for linear algebra and deep learning.

5.2 HIP and ROCm: AMD’s Answer#

AMD’s ROCm (Radeon Open Compute) ecosystem, coupled with the HIP (Heterogeneous-compute Interface for Portability) programming model, aims to achieve CUDA-like performance and portability. Developers can migrate CUDA code to HIP with minimal changes. While ROCm focuses primarily on Linux-based systems and data center-oriented workloads, the ecosystem is expanding.

5.3 OpenCL and Vulkan Compute#

For developers desiring an open, cross-vendor approach, OpenCL (Open Computing Language) remains a go-to solution. It provides a similar kernel-based model and memory management scheme, but is supported across different GPU vendors, CPUs, and even FPGAs.

Vulkan also includes a compute pipeline that can be utilized for GPU-accelerated workloads, potentially offering lower overhead than older graphics APIs with built-in compute functionalities.

6.1 Gaming and Real-Time Ray Tracing#

Modern games leverage GPUs to draw millions of polygons, apply complex shaders, and now, perform ray tracing in real time. Ray tracing simulates the behavior of light, producing more realistic reflections, shadows, and global illumination. Both NVIDIA and AMD now have hardware-accelerated ray tracing capabilities, although NVIDIA’s solution remains more mature and widely adopted in the early years of ray tracing adoption.

6.2 Machine Learning and HPC#

GPUs excel in tasks that involve matrix multiplication or large-scale linear algebra, making them indispensable for deep learning frameworks such as TensorFlow and PyTorch. From training large neural networks to performing high-speed scientific simulations, GPUs continue to power HPC clusters worldwide.

6.3 Professional Rendering and Content Creation#

Beyond gaming and AI, GPUs assist in professional 3D rendering (e.g., in movies, architectural visualization), video editing, and real-time encoding. Specialized drivers and features—like NVIDIA Studio drivers or AMD’s Pro drivers—offer optimized performance and stability for content creators.

7.1 Chiplet-Based Designs#

AMD has already introduced chiplet designs in its Ryzen CPUs, and with RDNA 3, they began to apply similar techniques to some GPUs. In this approach, the GPU die is broken into smaller, specialized chiplets (Graphics Compute Dies, Memory Cache Dies, etc.). This can reduce manufacturing costs, improve yields, and allow for more flexible scaling.

NVIDIA, too, is rumored to be exploring multi-chip module (MCM) designs for future data center GPUs, potentially enabling significant leaps in performance.

7.2 Multi-GPU Scaling#

While the mid-2000s saw consumer-level multi-GPU solutions like NVIDIA SLI and AMD CrossFire, the gaming industry has largely shifted away from these configurations because of driver and support complexities. However, in professional data centers and HPC environments, multi-GPU scaling is still critical. Advancements in interconnect technologies (NVLink, Infinity Fabric, PCIe Gen5 or beyond) will make multiple GPUs appear more like a single, large GPU resource.

7.3 Unified Memory and Advanced Interconnects#

Both NVIDIA (Unified Memory in CUDA) and AMD (Unified Addressing in ROCm and advanced Infinity Fabric) aim to simplify programming by blurring the lines between CPU and GPU memory. Future architectures will further reduce data transfer overheads, enable easier scaling across multiple computing devices, and pave the way for more seamless CPU-GPU integration.

7.4 AI-Enhanced Features#

Beyond using GPUs for AI workloads, there is a growing trend of GPUs internally using AI for tasks like super sampling (DLSS, FSR) and adaptive scheduling. Expect future architectures to incorporate more sophisticated on-die AI accelerators, possibly pushing real-time performance to new heights across gaming, graphics, and compute tasks.

8.1 CUDA Example: Vector Addition#

Below is a trivial CUDA vector addition program in C++.

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#include <iostream>
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__global__ void vectorAdd(const float* A, const float* B, float* C, int N) {
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    int i = blockDim.x * blockIdx.x + threadIdx.x;
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    if (i < N) {
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        C[i] = A[i] + B[i];
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    }
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}
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int main() {
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    int N = 1 << 20; // 1 million elements
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    size_t size = N * sizeof(float);
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    float *h_A, *h_B, *h_C;
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    h_A = new float[N];
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    h_B = new float[N];
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    h_C = new float[N];
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    for (int i = 0; i < N; i++) {
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        h_A[i] = 1.0f;
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        h_B[i] = 2.0f;
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    }
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    float *d_A, *d_B, *d_C;
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    cudaMalloc((void**)&d_A, size);
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    cudaMalloc((void**)&d_B, size);
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    cudaMalloc((void**)&d_C, size);
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    cudaMemcpy(d_A, h_A, size, cudaMemcpyHostToDevice);
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    cudaMemcpy(d_B, h_B, size, cudaMemcpyHostToDevice);
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    int threadsPerBlock = 256;
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    int blocksPerGrid = (N + threadsPerBlock - 1) / threadsPerBlock;
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    vectorAdd<<<blocksPerGrid, threadsPerBlock>>>(d_A, d_B, d_C, N);
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    cudaMemcpy(h_C, d_C, size, cudaMemcpyDeviceToHost);
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    // Verify result
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    for (int i = 0; i < 10; i++) {
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        std::cout << h_C[i] << " ";
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    }
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    cudaFree(d_A);
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    cudaFree(d_B);
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    cudaFree(d_C);
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    delete[] h_A;
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    delete[] h_B;
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    delete[] h_C;
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    return 0;
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}

8.2 AMD HIP Example: Vector Addition#

HIP syntax is very similar to CUDA, making porting straightforward.

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#include <iostream>
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#include <hip/hip_runtime.h>
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__global__ void vectorAdd(const float* A, const float* B, float* C, int N) {
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    int i = blockDim.x * blockIdx.x + threadIdx.x;
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    if (i < N) {
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        C[i] = A[i] + B[i];
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    }
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}
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int main() {
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    int N = 1 << 20;
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    size_t size = N * sizeof(float);
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    float *h_A, *h_B, *h_C;
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    h_A = new float[N];
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    h_B = new float[N];
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    h_C = new float[N];
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    for (int i = 0; i < N; i++) {
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        h_A[i] = 1.0f;
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        h_B[i] = 2.0f;
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    }
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    float *d_A, *d_B, *d_C;
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    hipMalloc((void**)&d_A, size);
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    hipMalloc((void**)&d_B, size);
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    hipMalloc((void**)&d_C, size);
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    hipMemcpy(d_A, h_A, size, hipMemcpyHostToDevice);
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    hipMemcpy(d_B, h_B, size, hipMemcpyHostToDevice);
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    dim3 threadsPerBlock(256);
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    dim3 blocksPerGrid((N + threadsPerBlock.x - 1) / threadsPerBlock.x);
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    hipLaunchKernelGGL(vectorAdd, blocksPerGrid, threadsPerBlock, 0, 0, d_A, d_B, d_C, N);
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    hipMemcpy(h_C, d_C, size, hipMemcpyDeviceToHost);
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    for (int i = 0; i < 10; i++) {
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        std::cout << h_C[i] << " ";
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    }
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    hipFree(d_A);
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    hipFree(d_B);
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    hipFree(d_C);
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    delete[] h_A;
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    delete[] h_B;
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    delete[] h_C;
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    return 0;
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}

8.3 Simple GPU Kernel in OpenCL#

For an open-standard approach, here’s a simple OpenCL kernel for vector addition:

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__kernel void vectorAdd(__global const float* A,
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                        __global const float* B,
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                        __global float* C) {
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    int i = get_global_id(0);
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    C[i] = A[i] + B[i];
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}

The host code in C/C++ would handle device selection, memory buffers, and kernel enqueuing. Overall, OpenCL offers more portability but can sometimes lag in vendor-specific optimizations.